1. Field of the Invention
The present invention is directed to a semiconductor integrated circuit and an electronic information device. More particularly, the present invention is directed to a semiconductor integrated circuit, such as an embedded IC, required to operate under a low power consumption, and an electronic information device equipped with the semiconductor integrated circuit.
2. Description of the Related Art
The reduction of power consumption in a semiconductor integrated circuit has long been a major objective. One of the ways to achieve it is a method of providing two modes, such as a normal operation mode and a stand-by mode, in a semiconductor integrated circuit in order to reduce power consumption in the circuit by shutting down a system clock during a period when the semiconductor integrated circuit can shut down its functions, such as when there are no key inputs for a while at a PDA (Personal Digital Assistance) terminal.
FIG. 8 is a diagram describing such a conventional semiconductor integrated circuit.
A semiconductor integrated circuit 200 operates with an operating voltage from a power supply circuit 201. The semiconductor integrated circuit 200 includes: a core power source terminal (VDD-CORE) 100a; an IO power source terminal (VDD-IO) 100b; and a grounded power source terminal (VSS) 100c. VDD-CORE voltage and VDD-IO voltage are supplied to the core power source terminal 100a and the IO power source terminal 100b, from corresponding terminals 101a and 101b of the power supply circuit 201.
The grounded power source terminal 100c of the semiconductor integrated circuit 200 and a grounded power source terminal 101c of the power supply circuit 201 are set with a grounding electric potential.
The semiconductor integrated circuit 200 includes: a function block 113, which is an internal circuit thereof, for executing various functions; and a processor 106 for controlling the operation of the function block 113. The function block 113 and the processor 106 are connected to each other through a bus. The semiconductor integrated circuit 200 also includes: a clock generator (CG) 112 for generating a system clock for operating the function block 113 and the processor 106; and a phase locked loop circuit (PLL circuit) 111 for determining a frequency of the system clock generated by the clock generator 112. The PLL circuit 111 is connected with a crystal oscillator 102 for generating a clock signal (i_CLK) to be supplied to the PLL circuit 111.
The semiconductor integrated circuit 200 also includes: stand-by canceling factor input terminals 105a, 105b . . . 105, into which wake-up signals (i_WAKEUP_1, i_WAKEUP_2, . . . i_WAKEUP_x) are inputted in accordance with a plurality of stand-by canceling factors 1, 2 . . . x; a stand-by canceling factor detecting circuit 107 for outputting a stand-by canceling signal based on the wakeup signals inputted in the terminals; and a mode switching circuit 208 for shutting down the PLL circuit 111 and the oscillator 102 based on the stand-by signals from the processor 106, and for canceling the shutdown state of the PLL circuit 111 and the oscillator 102, by the stand-by canceling signal from the stand-by canceling factor detecting circuit 107, to resume the operation.
The internal circuits constituting the semiconductor integrated circuit 200, that is to say, the various function block 113, processor 106, clock generator 112, PLL circuit 111, stand-by canceling factor detecting circuit 107 and mode switching circuit 208, are configured to operate with the VDD-CORE voltage. The semiconductor integrated circuit 200 also includes a circuit driven with the VDD-IO voltage, such as a drive circuit (not shown) which constitutes input and output terminals. Herein, the VDD-CORE voltage is 1.2V±0.1V, and the VDD-IO voltage is 1.8V±0.1V.
In the semiconductor integrated circuit 200 with the configuration described above, when the internal processor 106, for example, detects that there is no key input for a certain period of time, the processor 106 instructs the mode switching circuit 208 to switch its mode from a normal operation mode to a stand-by mode, using a mode switching signal. When the mode switching circuit 208 receives the mode switching signal from the processor 106, the mode switching circuit 208 shuts down the crystal oscillator 102 and the PLL circuit 111 to switch the operation mode from the normal operation mode to the stand-by mode.
On the other hand, the returning to the normal operation mode from the stand-by mode is performed by the semiconductor integrated circuit 200 itself upon detecting a key input. Herein, the stand-by canceling factor detecting circuit 107 in the semiconductor integrated circuit 200 detects the generation of a key input as one of the stand-by canceling factors, and instructs the mode switching circuit 208 to return to the normal operation mode from the stand-by mode using the stand-by canceling signal. Upon receiving the stand-by canceling signal, the mode switching circuit 208 allows the crystal oscillator 102 and the PLL circuit 111 to resume their operation. As a result, the operation mode of the semiconductor integrated circuit 200 is returned to the normal operation mode.
The reduction of power consumption in the semiconductor integrated circuit 200 has been conventionally achieved by the switching between the normal operation mode and the stand-by mode. In recent years, however, the miniaturizing of semiconductor integrated circuits has been advanced, and as a result, leakage current of the amount that is not negligible flows even when the system clock is shut down. Thus, a new problem of not being able to achieve as much reduction of power consumption as before has occurred even if the operation mode is switched to the stand-by mode.
As a method for coping with the problem, conceived are a method for restraining leakage current itself by turning off the power source of part of internal circuits in a semiconductor integrated circuit (Reference 1), and a method for restraining leakage current by supplying a voltage that is a little lower than a normal operating voltage during stand-by (Reference 2).    Reference 1: Japanese Laid-Open Publication No. 2002-132397    Reference 2: Japanese Laid-Open Publication No. 63-65714